… A simple modification of the modular pipeline multiplier allows it to do correct two’s complement
additions of partial products (Section III), so that two’s complement data words can be …

… multiplier with programmable coefficients, (2) sign magnitude/two's complement 4-bit serial
pipeline multiplier … 5-bit dynamically programmable adder/subtractor, (4) 2/SUP -K/ scaler; (5) …

… a serial output product in two's complement notation as well. … two's complement multiplication
algorithm is worked out, that allows cellular implementation of serial-pipeline multipliers …

… multiplier arrays in Section 5, and we discuss some advantages of our two's complement …
can ensure that path lengths of clock lines to all cells in each stage of pipeline are equal …

… of this multiplier. Last, we present a new design of the Lyon’s serial pipeline multiplier by …
compare its hardware complexity with that of the proposed serial/parallel pipeline multiplier. …

… -based multiplier array can be used in a pipeline form. This pipeline multiplier array is …
considerably fewer delay elements compared to previously reported pipeline multipliers. …

… With an optimal number of four series full adders per pipeline stage, all three multipliers
are capable of multiplying arbitrarily large numbers of two's complement 64 bit operands …

… methods to pipeline serial/parallel multipliers (SPMs), and … It reduces the area of some
bit-serial multiplier versions. … advantage to pipeline digit-serial versions of the multipliers, the …

… multiplier using m-bit cells. Then, we show how the same structure can work with two’s-complement …
We can then insert the appropriate number of pipeline registers into the module, as …

The authors propose a fast, area-efficient, bit-parallel systolic architecture for two's complement
multiplication, which can be implemented on a single VLSI chip. This architecture is more …