… Abstract—This paper presents a high-speed low-complexity modified … in the complex Booth
multiplier. The modified Booth algorithm is used widely for high speed multiplications. Since …

… Efficient hardware architectures of softmax layer are desired for high speed deep learning …
exponential and the logarithmic units, which have very high complexity, was presented in [10]. …

… Such a high clock speed largely benefited from significantly less routing complexity because
of … In this paper, we will present a low complexity FPGA implementation for a 8176-bit (4, 32)-…

… This paper presents a high-speed low-complexity RS decoder for the very high-speed
optical communications. A high-speed low-complexity PrME algorithm block was proposed and …

… for high-speed low-complexity … high-speed VLC link is easy and low-cost without complex
arithmetic and hardware. Our VLC link was a good solution for high-speed low-complexity VLC …

… HT-EBdf with time complexity Oš1Ž is guaranteed to sustain high-speed operations. The
area… area and speed advantages over previous works and provide a high-speed, lowcomplexity …

… The low complexity of the implementation of the system is very attractive. Since we do not
need any high speed … and lowcomplexity implementations because of the lower computational …

… a high data throughput and low hardware complexity by using … to reduce the number of
complex multiplications and twiddle … smaller hardware complexity and low power consumption. …

… lead to a significant reduction in hardware complexity. The organization of the paper is as …
to design low complexity DFE architecture. In Section 4, the hardware complexities needed …

… high-speed low-complexity two-parallel decoder architecture for 100 Gb/s optical communication
systems. Also, a low-complexity … of reducing the hardware complexity and improving the …