The pipeline form of the serial/parallel multiplier for constant numbers, which operates
without insertion of zero words between successive data, is presented. The constant number …

An efficient implementation of a complex number serial multiplier, when the one factor is
constant, is presented. The real and imaginary parts of the constant number are represented …

Bit-serial algorithms for arithmetic operations (ie addition, multiplication) are suitable for
efficient VLSI implementation because of their canonical structure and minimal …

This paper describes the design of a 16× 16 redundant binary multiplier for signed 2's
complement numbers. The multiplier uses a new coding scheme for representing radix-2 …

A fast serial-parallel multiplier based on the Baugh-Wooley algorithm is proposed. It is
shown that sign extension of the sum or carry bit, produced during the addition of the bit …

High-speed multipliers are essential building blocks for modern computers, signal
processing and other digital systems. A new parallel multiplier configuration is developed in …

A new algorithm for the multiplication of two n-bit numbers based on the synchronous
computation of the partial sums of the two operands is presented. The proposed algorithm …

A new cell architecture for high performance digit-serial computation is presented. The
design of this cell is based on the feed forward of the carry digit, which allows a high level of …

A new bit serial-serial multiplier for unsigned numbers is presented in this paper. The
numbers being multiplied enter the circuit simultaneously in LSB first bit-serial form. The …

This paper presents the design of a new multiplier architecture for normal integer
multiplication of positive and negative numbers. It has been developed to increase the …