Although parallel multipliers are optimal for speed, they occupy considerable chip area. For
applications with lengthy operands as cryptography, the required area grows further. On the …

Digit-serial implementation styles are best suited for implementation of digital signal
processing systems which require moderate sampling rates. Digit-serial architectures …

A novel low latency, most significant digit-first, signed digit multiplier architecture is
presented. The design of the multiplier is based on a new 2 bit adder cell. Judicious …

Digit-serial/parallel multipliers with improved throughput and latency are presented. The
multipliers are based on unfolded bit-serial/parallel multipliers. The unfolding yields long …

Digit-serial implementation styles are best suited for implementation of digital signal
processing systems which require moderate sampling rates. Digit-serial multipliers obtained …

Efficient architecture of low-complexity digit serial GF (2 m) multiplier using dual basis
representation is proposed in this paper. The architecture of digit serial multiplier is suitable …

A Novel architecture of low-complexity digit serial GF (2 m) multiplier using dual basis
representation is proposed in this paper. The architecture of digit serial multiplier is suitable …

In this paper, the method which improves the performance of a serial decimal multiplier, and
the method which operates multiple-digit simultaneously are proposed. The proposed serial …

Digit serial–serial multipliers are one approach to power-optimize multiplication where
operands are fed one digit at a time. This significantly reduces the required chip area and …

A new serial-serial multiplier is being proposed which requires only N/2 conventional cells
for multiplying two N-bit numbers, compared to N cells needed in existing structures. The …