Challenges in the implementation of low-k dielectrics in the back-end of line
The introduction of ultra low-k materials in copper technology has been much slower than
anticipated in the ITRS Roadmap. The introduction of porosity in low-k materials has …
anticipated in the ITRS Roadmap. The introduction of porosity in low-k materials has …
Challenges of back end of the line for sub 65 nm generation
M Fayolle, G Passemard, O Louveau, F Fusalba… - Microelectronic …, 2003 - Elsevier
This paper presents a review of interconnect challenges for sub 65 nm node. From this
generation, porous ultra low K (ULK) dielectric materials (dielectric constant k< 2.1) are …
generation, porous ultra low K (ULK) dielectric materials (dielectric constant k< 2.1) are …
[HTML][HTML] Progress in the development and understanding of advanced low k and ultralow k dielectrics for very large-scale integrated interconnects—State of the art
The improved performance of the semiconductor microprocessors was achieved for several
decades by continuous scaling of the device dimensions while using the same materials for …
decades by continuous scaling of the device dimensions while using the same materials for …
Evaluation of ultra-low-k dielectric materials for advanced interconnects
Abstract The International Technology Roadmap for Semiconductors predicts that continued
scaling of devices will require ultra-low-k materials with k values less than 2.5 for the 100 nm …
scaling of devices will require ultra-low-k materials with k values less than 2.5 for the 100 nm …
Integration challenges of porous ultra low-k spin-on dielectrics
K Mosig, T Jacobs, K Brennan, M Rasco, J Wolf… - Microelectronic …, 2002 - Elsevier
In the latest edition of the International Technology Roadmap for Semiconductors (ITRS), the
predicted time for the introduction of porous ultra low-k materials with a dielectric constant of …
predicted time for the introduction of porous ultra low-k materials with a dielectric constant of …
Electrical reliability challenges of advanced low-k dielectrics
We review the latest studies that address the fundamental understanding of low-k dielectric
electrical properties and reliability. We focus on the results discussing the nature of process …
electrical properties and reliability. We focus on the results discussing the nature of process …
Characterization and integration of a CVD porous SiOCH (k< 2.5) with enhanced mechanical properties for 65 nm CMOS interconnects and below
LL Chapelon, V Arnal, M Broekaart, LG Gosset… - Microelectronic …, 2004 - Elsevier
Device performance for 65 nm node CMOS technology and beyond will require the
integration of porous ultra-low-k materials with dielectric constant below 2.5, in order to …
integration of porous ultra-low-k materials with dielectric constant below 2.5, in order to …
Mechanical stability of porous low-k dielectrics
This paper reviews the mechanical and fracture properties of porous ultralow-k dielectrics
with the focus on chip package interaction related issues. It is shown that the mechanical …
with the focus on chip package interaction related issues. It is shown that the mechanical …
Copper interconnects for semiconductor devices
SM Merchant, SH Kang, M Sanganeria… - Jom, 2001 - Springer
Copper/low-k dielectric materials have been rapidly replacing conventional aluminum-
alloy/SiO 2-based interconnects in today's semiconductor devices. This paper reviews the …
alloy/SiO 2-based interconnects in today's semiconductor devices. This paper reviews the …
Sidewall restoration of porous ultra low-k dielectrics for sub-45 nm technology nodes
H Chaabouni, LL Chapelon, M Aimadeddine… - Microelectronic …, 2007 - Elsevier
Plasma ashing and etching integration steps on porous ultra low-k (ULK) have been
investigated and are found to damage the porous dielectric structural and electrical …
investigated and are found to damage the porous dielectric structural and electrical …