Routing algorithms for cache-coherent NoCs only have limited VCs at their disposal, which
poses challenges to the design of routing algorithms. Existing fully adaptive routing …

Routing algorithms for networks-on-chip (NoCs) typically only have a small number of virtual
channels (VCs) at their disposal. Limited VCs pose several challenges to the design of fully …

As the number of applications and programmable units in CMPs and MPSoCs increases, the
Network-on-Chip (NoC) encounters diverse and time dependent traffic loads. This trend …

Routing algorithm has a significant impact on the overall performance of network-on-chip
(NoC) based system due to the unbalanced nature of NoC traffic. In this paper, we propose …

Deterministic routing algorithms are easier to design and implement in NoC but these fail to
adapt to congestion. Table based adaptive routing solutions are not scalable. As the number …

Buffer resource minimization plays an important role to achieve power-efficient NoC
designs. At the same time, advanced switching mechanisms like virtual cut-through (VCT) …

A basic design aspect of cache coherent Networks-on-Chip (NoCs) is the flow control
mechanism. Since the minimum buffer size of virtual cut-through (VCT) switching is larger …

A novel routing algorithm, named Balanced Adaptive Routing Protocol (BARP), is proposed
for NoCs to provide adaptive routing and ensure deadlock-free and livelock-free routing at …

Silicon devices are becoming less and less reliable as technology moves to smaller feature
sizes. As a result, digital systems are increasingly likely to experience permanent failures …

Future applications will require processors with many cores communicating through a
regular interconnection network. As the semiconductor industry advances to the deep sub …