Microprocessor designers have been torn between tight constraints on the amount of on-
chip cache memory and the high latency of off-chip memory, such as dynamic random …

Cache compression is a promising technique to increase on-chip cache capacity and to
decrease on-chip and off-chip bandwidth usage. Unfortunately, directly applying well-known …

Cache memories play a critical role in bridging the latency, bandwidth, and energy gaps
between cores and off-chip memory. However, caches frequently consume a significant …

Proposed cache compression schemes make design-time assumptions on value locality to
reduce decompression latency. For example, some schemes assume that common values …

Low utilization of on-chip cache capacity limits performance and wastes energy because of
the long latency, limited bandwidth, and energy consumption associated with off-chip …

Memory is one of the most restricted resources in many modern embedded systems. Code
compression can provide substantial savings in terms of size. In a compressed code CPU, a …

Modern processors use two or more levels ofcache memories to bridge the rising disparity
betweenprocessor and memory speeds. Compression canimprove cache performance by …

The effectiveness of a compressed cache depends on three features: i) the compression
scheme, ii) the compaction scheme, and iii) the cache layout of the compressed cache …

With the widening gap between processor and memory speeds, memory system designers
may find cache compression beneficial to increase cache capacity and reduce off-chip …

This paper contributes a novel approach for reducing static code size and instruction fetch
energy for cache-based core processors running embedded applications. Our …