Applications & Technology Page 1 International Conference On Signal Processing
Applications & Technology TIT Page 2 High Speed and Very Compact Two's Complement …

This paper presents a new multiplier design which is fully-serial and requires only 1.5 N
cycles to return a product. This design has been implemented for both unsigned and two's …

The pipeline form of the serial/parallel multiplier for constant numbers, which operates
without insertion of zero words between successive data, is presented. The constant number …

This paper presents an optimized design approach for two's complement large size
multipliers using smaller size embedded multiplier blocks available as resources in field …

This paper presents the design and implementation of signed-unsigned Modified Booth
multiplier. The present MBE multiplier and Baugh-wooley multi-pliers performs multiplication …

The basic building block of DSP-based implementation is multipliers. There are many
multiplier structures suitable for VLSI implementation. In this paper, a new structure is …

A fast serial-parallel multiplier based on the Baugh-Wooley algorithm is proposed. It is
shown that sign extension of the sum or carry bit, produced during the addition of the bit …

A new apparatus for fast multiplication of two numbers is introduced. Inputs are split into
partitions, and one number is replaced by two with zeros interlaced in every other partition …

Three serial/parallel multipliers are introduced, which both receive the serial input data and
produce the serial product in a most-significant-bit-first (MSB-first) fashion. Advantages of …

A serial-parallel multiplier for two's complement numbers is proposed. Based on an efficient
two's complement multiplication algorithm, the proposed multiplier is composed of …