Design of low-error fixed-width multiplier for DSP applications
JM Jou, SR Kuang - Electronics Letters, 1997 - IET
A low-error design of the fixed-width parallel multiplier for digital signal processing (DSP)
applications is proposed. Applying two n bit inputs, it generates the n bit, instead of 2n bit …
applications is proposed. Applying two n bit inputs, it generates the n bit, instead of 2n bit …
Design of low-error fixed-width multipliers for DSP applications
JM Jou, SR Kuang, R Der Chen - IEEE Transactions on …, 1999 - ieeexplore.ieee.org
In this work, two designs of low-error fixed-width sign-magnitude parallel multipliers and
two's-complement parallel multipliers for digital signal processing applications are …
two's-complement parallel multipliers for digital signal processing applications are …
Low error truncated multipliers for DSP applications
V Garofalo, N Petra, D De Caro… - 2008 15th IEEE …, 2008 - ieeexplore.ieee.org
The paper presents a new technique to design signed and unsigned truncated multipliers.
Simple formulae are developed in the paper to describe the truncated multiplier with …
Simple formulae are developed in the paper to describe the truncated multiplier with …
Area-efficient multipliers for digital signal processing applications
SS Kidambi, F El-Guibaly… - IEEE Transactions on …, 1996 - ieeexplore.ieee.org
An area-efficient parallel sign-magnitude multiplier that receives two N-bit numbers and
produces an N-bit product, referred to as a truncated multiplier, is described. The …
produces an N-bit product, referred to as a truncated multiplier, is described. The …
Design of high-speed low-power 3-2 counter and 4-2 compressor for fast multipliers
Hsiao, Jiang, Yeh - Electronics Letters, 1998 - IET
A 3-2 counter and a 4-2 compressor are the basic components in the partial product
summation tree of a parallel array multiplier. A new high-speed and low-power design of …
summation tree of a parallel array multiplier. A new high-speed and low-power design of …
Low power parallel multiplier design for DSP applications through coefficient optimization
Digital Signal Processing (DSP) often involves multiplications with a set of coefficients. This
paper presents a novel multiplier design methodology for performing these coefficient …
paper presents a novel multiplier design methodology for performing these coefficient …
Generalized low-error area-efficient fixed-width multipliers
LD Van, CC Yang - IEEE Transactions on Circuits and Systems …, 2005 - ieeexplore.ieee.org
In this paper, we extend our previous methodology for designing a family of low-error area-
efficient fixed-width two's-complement multipliers that receive two n-bit numbers and …
efficient fixed-width two's-complement multipliers that receive two n-bit numbers and …
Design of the lower error fixed-width multiplier and its application
LD Van, SS Wang, WS Feng - IEEE Transactions on Circuits …, 2000 - ieeexplore.ieee.org
This brief develops a general methodology for designing a lower-error two's-complement
fixed-width multiplier that receives two n-bit numbers and produces an n-bit product. By …
fixed-width multiplier that receives two n-bit numbers and produces an n-bit product. By …
Fast FPGA-based pipelined digit-serial/parallel multipliers
In this paper fast pipelined digit-serial/parallel multipliers are proposed. The conventional
digit-serial/parallel multipliers and their pipelined versions are presented. Every structure …
digit-serial/parallel multipliers and their pipelined versions are presented. Every structure …
Low-error configurable truncated multipliers for multiply-accumulate applications
SR Kuang, JP Wang - Electronics letters, 2006 - IET
A configurable error-compensation circuit for truncated parallel multipliers is proposed. The
proposed circuit is capable of being configured to minimise either the mean error or the …
proposed circuit is capable of being configured to minimise either the mean error or the …