Traditional serial-serial multiplier structures suffer from an inefficient generation of partial
products, which leads to hardware overuse and slow speed systems. In this paper, two new …

A new serial-serial multiplier is being proposed which requires only N/2 conventional cells
for multiplying two N-bit numbers, compared to N cells needed in existing structures. The …

All serial–serial multiplication structures previously reported in the literature have been
confined to bit serial–serial multipliers. An architecture for digit serial–serial multipliers is …

A new cell architecture for high performance digit-serial computation is presented. The
design of this cell is based on the feed forward of the carry digit, which allows a high level of …

A fast serial-parallel multiplier based on the Baugh-Wooley algorithm is proposed. It is
shown that sign extension of the sum or carry bit, produced during the addition of the bit …

A fast serial-parallel (FSP) multiplier design is derived from the carry-save add-shift (CSAS)
multiplier structure. The CSAS technique accepts multiplier bits serially (lsb first) and …

In this article partial products algorithm of serial multipliers is presented and different
architectures of these kinds of multipliers such as: Successive Addition, Serial-Parallel and …

A new bit serial-serial multiplier for unsigned numbers is presented in this paper. The
numbers being multiplied enter the circuit simultaneously in LSB first bit-serial form. The …

The paper proposes a systematic design methodology for bit-serial multiplication. The
proposed approach is a modified method for performing traditional multiplication. This paper …

Digit-serial architectures obtained using traditional unfolding and folding techniques cannot
be pipelined beyond a certain level because of the presence of feedback loops. In this …