The basic building block of DSP-based implementation is multipliers. There are many
multiplier structures suitable for VLSI implementation. In this paper, a new structure is …

This paper describes the design of a 16× 16 redundant binary multiplier for signed 2's
complement numbers. The multiplier uses a new coding scheme for representing radix-2 …

Constant-coefficient multipliers are used in many DSP cores. A new low-power constant
multiplier, with detailed design procedure, is presented. By using canonical sign-digit (CSD) …

A generator for multiplier and squarer structures, suitable for high performance bit-parallel
DSP applications in VLSI, is presented. The squarer structure employs a novel bit-parallel …

Low power parallel array multiplier is proposed for both unsigned and two's complement
signed multiplication. Modified Baugh-Wooley multiplier is further modified and if input …

This paper presents the methods required to implement a high speed and high performance
parallel complex number multiplier. The designs are structured using Radix-4 Modified …

A high speed multiplier design is presented using redundant binary signed-digit number
representation internally while the input operands and the output product are in two's …

Applications & Technology Page 1 International Conference On Signal Processing
Applications & Technology TIT Page 2 High Speed and Very Compact Two's Complement …

Multiplication is one of the basic and critical operations in the computations. Efficient
implementations of multipliers are required in many applications. In this paper, a new …

A new bit serial-serial multiplier for unsigned numbers is presented in this paper. The
numbers being multiplied enter the circuit simultaneously in LSB first bit-serial form. The …