A fine time-resolution (≪ 3 ps-rms) time-to-digital converter for highly integrated designs

L Perktold, J Christiansen - 2013 IEEE International …, 2013 - ieeexplore.ieee.org
A multi-channel 3-ps-rms single-shot precision timeto-digital converter (TDC) is presented.
The time interpolation is based on a delay-locked-loop (DLL) employing resistive …

Wide-range time-to-digital converter with 1-ps single-shot precision

P Keranen, K Maatta… - IEEE transactions on …, 2011 - ieeexplore.ieee.org
A high-resolution time-to-digital converter (TDC) was designed and tested. The converter is
based on the fundamental method of counting the full clock cycles of a low-phase-noise …

Monolithic time-to-digital converter with 20ps resolution

S Tisa, A Lotito, A Giudice… - ESSCIRC 2004-29th …, 2003 - ieeexplore.ieee.org
We present a fully-integrated time-to-digital converter, in a standard 0.8/spl mu/m-CMOS
technology, based on a cyclic pulse-shrinking design, that provides the lowest channel width …

Time-to-digital converter with 2.1-ps RMS single-shot precision and subpicosecond long-term and temperature stability

D Vyhlidal, M Cech - IEEE Transactions on Instrumentation and …, 2015 - ieeexplore.ieee.org
This paper presents the design and performance measurement results of a prototype time-to-
digital converter (TDC) implemented using commercially available components. The TDC is …

An integrated CMOS high precision time-to-digital converter based on stabilised three-stage delay line interpolation

A Mäntyniemi - 2004 - oulurepo.oulu.fi
This thesis describes the development of a high precision time-to-digital converter (TDC) in
which the conversion is based on a counter and three-stage stabilised delay line …

90nm 4.7 ps-resolution 0.7-LSB single-shot precision and 19pJ-per-shot local passive interpolation time-to-digital converter with on-chip characterization

S Henzler, S Koeppe, W Kamp, H Mulatz… - … Solid-State Circuits …, 2008 - ieeexplore.ieee.org
Time-to-digital converters (TDC) support the industry wide trend of replacing mixed-signal
functionality by digital realizations. High-resolution TDCs become increasingly popular for …

A multichannel time-to-digital converter ASIC with better than 3 ps RMS time resolution

L Perktold, J Christiansen - Journal of Instrumentation, 2014 - iopscience.iop.org
The development of a new multichannel, fine-time resolution time-to-digital converter (TDC)
ASIC is currently under development at CERN. A prototype TDC has been designed …

A high-resolution (< 10 ps RMS) 32-channel time-to-digital converter (TDC) implemented in a field programmable gate array (FPGA)

E Bayer, M Traxler - 2010 17th IEEE-NPSS Real Time …, 2010 - ieeexplore.ieee.org
A high-resolution 32-Channel Time-to-Digital Converter (TDC) implemented in a general
purpose Field Programmable Gate Array (FPGA) is presented. Dedicated carry chains of the …

A 16 mW 250 ps double-hit-resolution input-sampled time-to-digital converter in 45-nm CMOS

SU Rehman, MM Khafaji, C Carta… - IEEE Transactions on …, 2018 - ieeexplore.ieee.org
Several new approaches for multi-hit delay-line-based time-to-digital converters (TDCs) are
discussed and an input-sampled TDC architecture is realized in 45-nm SOI CMOS. The TDC …

A 23ps resolution Time-to-Digital converter implemented on low-cost FPGA platform

M Abbas, K Khalil - … on Signals, Circuits and Systems (ISSCS), 2015 - ieeexplore.ieee.org
This paper presents a low-cost implementation and measurement setup of an accurate Time-
to-Digital converter (TDC). The design was realized using ring oscillator-based TDC …