The paper describes the architecture of a binary multiplier that, because of its intrinsic
regularity and simplicity, may be extended for any number of bits. It is a modification of the …

A scheme for a fully-systolic bit-serial multiplier is presented, based on merging two adjacent
cells of an existing semi-systolic multiplier in a single new cell. The multiplier has immediate …

This paper presents a new multiplier design which is fully-serial and requires only 1.5 N
cycles to return a product. This design has been implemented for both unsigned and two's …

This paper describes the design of a 16× 16 redundant binary multiplier for signed 2's
complement numbers. The multiplier uses a new coding scheme for representing radix-2 …

We consider the problem of adding the partial products in the combinational decimal
multiplier presented by Lang and Nannarelli. In the original paper this addition is done with …

In this article we consider a design of a multiplier for the multiplication of complex numbers.
The complex numbers are packed into one 32-bit word. They are represented by two 13-bit …

With a suitable adder organization it is possible to overlap the adder operation during a
binary multiplication and significantly decrease the overall multiplication time. The method is …

This paper presents four new arrays for signed number multiplication and
multiplication/addition. In these structures, it is assumed that the factors are expressed in 2's …

A bit-parallel systolic multiplier based on pair-wise grouping of the bit products is presented.
The proposed scheme yields significantly lower latency compared to existing systolic …

In this paper two new schemes of systolic multipliers are proposed, one based on Modified
Booth encoding and the other is based on the selection of one of the terms 0, X, 2X, 3X …