New parallel multiplier design
MC Mekhallalati, MK Ibrahim - Electronics Letters, 1992 - IET
A new parallel multiplier structure is proposed. In this multiplier the operands are partitioned
into four groups of bits to produce 16 partial product terms. The novelty of the new structure …
into four groups of bits to produce 16 partial product terms. The novelty of the new structure …
Two's complement parallel multiplier
A Aggoun - Electronics Letters, 1998 - IET
A new two's complement parallel multiplier architecture is proposed. It is based on the
partitioning of one of the operands into four groups. Array multipliers without the final adder …
partitioning of one of the operands into four groups. Array multipliers without the final adder …
Suggestion for an IC fast parallel multiplier
R De Mori - Electronics letters, 1969 - IET
Suggestion for an ic fast parallel multiplier Page 1 system so as to make the thicker end an
anode, the travelling domain-mode current oscillation disappeared, and the current …
anode, the travelling domain-mode current oscillation disappeared, and the current …
New architecture for parallel multipliers
Z Wang, GA Jullien, WC Miller - Electronics Letters, 1992 - IET
An architecture for parallel multipliers, based on 2 bit full adders, is proposed. Multipliers
built in this way possess the same structure as previously published five-counter multipliers …
built in this way possess the same structure as previously published five-counter multipliers …
Faster parallel multiplier
A Dhurkadas - Proceedings of the IEEE, 1984 - ieeexplore.ieee.org
Realization of a parallel multiplier has been considered in a paper by Dadda [1] who has
proposed various schemes to get the product using (3, 2),(2, 2) counters, and carry look …
proposed various schemes to get the product using (3, 2),(2, 2) counters, and carry look …
Fast multiplier design using redundant signed-digit numbers
TN Rajashekhara, O Kal - International Journal of Electronics …, 1990 - Taylor & Francis
A high speed multiplier design is presented using redundant binary signed-digit number
representation internally while the input operands and the output product are in two's …
representation internally while the input operands and the output product are in two's …
Radix-4 multiplier with regular layout structure
Park, Shin, Park, Kyung - Electronics Letters, 1998 - IET
A new parallel multiplier with a regular layout structure is described. To achieve a regular
structure without sacrificing performance, a new circuit called the weighted carry save adder …
structure without sacrificing performance, a new circuit called the weighted carry save adder …
Part 1: VLSI implementation of an optimised hierarchical multiplier
HC Yung, CR Allen - IEE Proceedings G (Electronic Circuits and Systems), 1984 - IET
The implementation and optimisation procedure of a regular, and recursive, high-speed N-
bit multiplier design is presented. The design comprises two simple cells: a 2× 2-bit …
bit multiplier design is presented. The design comprises two simple cells: a 2× 2-bit …
A single chip parallel multiplier by MOS technology
S Nakamura, KY Chu - IEEE transactions on computers, 1988 - ieeexplore.ieee.org
A parallel multiplier design based on the five-counter cell is discussed. A design
optimization for the performance in speed is proposed at the logic design level which is …
optimization for the performance in speed is proposed at the logic design level which is …
New parallel multipliers based on low power adders
R Mudassir, Z Abid - Canadian Conference on Electrical and …, 2005 - ieeexplore.ieee.org
Two new parallel multiplier architectures are designed based on two new full adders. These
two adders are based on a new algorithm and display low power dissipation and high …
two adders are based on a new algorithm and display low power dissipation and high …