CMOS scaling enabled simultaneous system throughput scaling by concurrent delay, power,
and area shrinks with thanks to Moore's law. System scaling is getting more difficult with the …

The system driver models for microprocessor (MPU) and system-on-chip (SOC) in the
International Technology Roadmap for Semiconductors [21](ITRS) determine the roadmap …

Design cost and power/energy have been major challenges for the semiconductor industry
over the past decade or more. Increase in gate count, driven by scaling of physical …

The International Technology Roadmap for Semiconductors (ITRS) has roadmapped
technology requirements of the semiconductor industry over the past two decades. The …

The DeSyRe project builds on-demand adaptive and reliable Systems-on-Chips (SoCs). As
fabrication technology scales down, chips are becoming less reliable, thereby incurring …

This paper is a tutorial-style introduction to a special session on: Effective Voltage Scaling in
the Late CMOS Era. It covers the fundamental challenges and associated solution strategies …

Defining a processor micro-architecture for a targeted productspace involves multi-
dimensional optimization across performance, power and reliability axes. A key decision in …

The imminent end of Moore's Law demands increasing complexi-ty to enable continuing
improvement in the cost and performance of electronic systems. Complex RTL designs lead …

CMOS scaling so far enabled simultaneous system throughput scaling by concurrent
improvements in delay, power, and area with thanks to Moore's law. CMOS scaling becomes …

The energy efficiency of a CMOS architecture processing dynamic workloads directly affects
its ability to provide long battery lifetimes while maintaining required application …