Pipelined serial/parallel multiplier with contraflowing data streams
MB Tošić, MK Stojčev - Electronics Letters, 1991 - IET
An improved architecture of the Muller pipeline serialparallel multiplier is presented. The
proposed solution is based on the integration of two Muller cells into one. This modification …
proposed solution is based on the integration of two Muller cells into one. This modification …
Novel pipelined serial/parallel multiplier
D Ait-Boudaoud, MK Ibrahim, BR Hayes-Gill - Electronics Letters, 1990 - IET
Novel pipelined serial/parallel multiplier Page 1 from eqn. 10, p is approximately four times d
so the minimum ax is realised. Fig. 3 shows the theoretical and experimental insertion losses …
so the minimum ax is realised. Fig. 3 shows the theoretical and experimental insertion losses …
Two's complement parallel multiplier
A Aggoun - Electronics Letters, 1998 - IET
A new two's complement parallel multiplier architecture is proposed. It is based on the
partitioning of one of the operands into four groups. Array multipliers without the final adder …
partitioning of one of the operands into four groups. Array multipliers without the final adder …
Cellular two's complement serial—pipeline multipliers
KZ Pekmestzi, GD Papadopoulos - Radio and Electronic Engineer, 1979 - IET
Serial two's complement pipeline multipliers are the basic module in the serial arithmetic
implementation of digital signal processing algorithms. These multipliers accept the data …
implementation of digital signal processing algorithms. These multipliers accept the data …
Constant number serial pipeline multipliers
KZ Pekmestzi, P Kalivas - Journal of VLSI signal processing systems for …, 2000 - Springer
The pipeline form of the serial/parallel multiplier for constant numbers, which operates
without insertion of zero words between successive data, is presented. The constant number …
without insertion of zero words between successive data, is presented. The constant number …
Design of low-error fixed-width multiplier for DSP applications
JM Jou, SR Kuang - Electronics Letters, 1997 - IET
A low-error design of the fixed-width parallel multiplier for digital signal processing (DSP)
applications is proposed. Applying two n bit inputs, it generates the n bit, instead of 2n bit …
applications is proposed. Applying two n bit inputs, it generates the n bit, instead of 2n bit …
Hybrid low-latency serial-parallel multiplier architecture
A novel low latency, most significant digit-first, signed digit multiplier architecture is
presented. The design of the multiplier is based on a new 2 bit adder cell. Judicious …
presented. The design of the multiplier is based on a new 2 bit adder cell. Judicious …
New parallel multiplier design
MC Mekhallalati, MK Ibrahim - Electronics Letters, 1992 - IET
A new parallel multiplier structure is proposed. In this multiplier the operands are partitioned
into four groups of bits to produce 16 partial product terms. The novelty of the new structure …
into four groups of bits to produce 16 partial product terms. The novelty of the new structure …
Regular pipelined multipliers
W Luk - Electronics Letters, 1989 - IET
Regular pipelined multipliers Page 1 ties drastically. !>,•,_„ increased by 3-5 x 1011 and 1-5 x
1011cm~2eV~1 in the RTN and control oxide samples, respectively, after 5 Mrad (Si). However …
1011cm~2eV~1 in the RTN and control oxide samples, respectively, after 5 Mrad (Si). However …
Bit-level pipelined digit-serial multiplier
A new cell architecture for high performance digit-serial computation is presented. The
design of this cell is based on the feed forward of the carry digit, which allows a high level of …
design of this cell is based on the feed forward of the carry digit, which allows a high level of …