Low-hardware consumption, resolution-configurable gray code oscillator time-to-digital converters implemented in 16 nm, 20 nm, and 28 nm FPGAs
This article presents a low-hardware consumption, resolution-configurable, automatically
calibrating gray code oscillator time-to-digital converter (TDC) in Xilinx 16-nm UltraScale+ …
calibrating gray code oscillator time-to-digital converter (TDC) in Xilinx 16-nm UltraScale+ …
Ring-oscillator-based high accuracy low complexity multichannel time-to-digital converter architecture for field-programmable gate arrays
S Berrima, Y Blaquière… - IEEE Transactions on …, 2021 - ieeexplore.ieee.org
This article proposes and validates a low complexity multichannel ring-oscillator (RO)-based
time-to-digital converter (TDC) architecture for field-programmable gate arrays (FPGAs) …
time-to-digital converter (TDC) architecture for field-programmable gate arrays (FPGAs) …
A low nonlinearity, missing-code free time-to-digital converter based on 28-nm FPGAs with embedded bin-width calibrations
H Chen, Y Zhang, DDU Li - IEEE Transactions on …, 2017 - ieeexplore.ieee.org
This paper presents a low nonlinearity, missing-code free, time-to-digital converter (TDC)
implemented in a 28-nm field programmable gate array (FPGA) device (Xilinx Virtex 7 …
implemented in a 28-nm field programmable gate array (FPGA) device (Xilinx Virtex 7 …
A Two-Stage Interpolation Time-to-Digital Converter Implemented in 20 and 28 N· m FGPAs
Y Wang, W Xie, H Chen, C Pei… - IEEE Transactions on …, 2024 - ieeexplore.ieee.org
This article presents a two-stage interpolation time-to-digital converter (TDC), combining a
Vernier gray code oscillator TDC (VGCO-TDC) and a tapped-delay line TDC (TDL-TDC) …
Vernier gray code oscillator TDC (VGCO-TDC) and a tapped-delay line TDC (TDL-TDC) …
Multichannel, low nonlinearity time-to-digital converters based on 20 and 28 nm FPGAs
H Chen, DDU Li - IEEE Transactions on Industrial Electronics, 2018 - ieeexplore.ieee.org
This paper presents low nonlinearity, compact, and multichannel time-to-digital converters
(TDC) in Xilinx 28 nm Virtex 7 and 20 nm UltraScale field-programmable gate arrays …
(TDC) in Xilinx 28 nm Virtex 7 and 20 nm UltraScale field-programmable gate arrays …
TwinPop: A Resource-efficient and Highly Linear FPGA-based Time-to-Digital Converter
The field programmable gate array (FPGA)-based time-to-digital converter (TDC) has been
notoriously troubled by its nonlinearity problems. To address it, conventional approaches …
notoriously troubled by its nonlinearity problems. To address it, conventional approaches …
Novel nonlinearity minimized time-to-digital converters with digital calibration technique
This paper presents a low nonlinearity, four channel Gated Ring Oscillator (GRO) based
Time-to-Digital Converters (TDC) in Xilinx 28 nm Virtex 7 Field Programmable Gate Arrays …
Time-to-Digital Converters (TDC) in Xilinx 28 nm Virtex 7 Field Programmable Gate Arrays …
Multi-channel FPGA time-to-digital converter with 10 ps bin and 40 ps FWHM
D Portaluppi, K Pasquinelli, I Cusini… - IEEE Transactions on …, 2022 - ieeexplore.ieee.org
We present a novel architecture for multi-channel time-to-digital converters (TDCs) to be
implemented into low-cost field-programmable gate arrays (FPGAs), achieving 10-ps least …
implemented into low-cost field-programmable gate arrays (FPGAs), achieving 10-ps least …
High-resolution time-to-digital converters implemented on 40-, 28-, and 20-nm FPGAs
M Zhang, K Yang, Z Chai, H Wang… - IEEE Transactions on …, 2020 - ieeexplore.ieee.org
This work proposed the implementations of high-resolution time-to-digital converters (TDCs)
on field-programmable gate array (FPGA) platforms with different manufacturing …
on field-programmable gate array (FPGA) platforms with different manufacturing …
An efficient TDC using a dual-mode resource-saving method evaluated in a 28-nm FPGA
M Parsakordasiabi, I Vornicu… - IEEE Transactions …, 2021 - ieeexplore.ieee.org
FPGA-based time-to-digital converters (TDCs) are required to be accurate, linear, and fast,
while at the same time employing a reduced number of resources. Pushing these …
while at the same time employing a reduced number of resources. Pushing these …