90nm 4.7 ps-resolution 0.7-LSB single-shot precision and 19pJ-per-shot local passive interpolation time-to-digital converter with on-chip characterization

S Henzler, S Koeppe, W Kamp, H Mulatz… - … Solid-State Circuits …, 2008 - ieeexplore.ieee.org
Time-to-digital converters (TDC) support the industry wide trend of replacing mixed-signal
functionality by digital realizations. High-resolution TDCs become increasingly popular for …

A 1.7 mW 11b 1–1–1 MASH ΔΣ time-to-digital converter

Y Cao, P Leroux, W De Cock… - 2011 IEEE International …, 2011 - ieeexplore.ieee.org
Recently, high-resolution TDCs have gained more and more popularity due to their
increasing implementation in digital PLLs, ADCs, jitter measurement and time-of-flight …

A fine time-resolution (≪ 3 ps-rms) time-to-digital converter for highly integrated designs

L Perktold, J Christiansen - 2013 IEEE International …, 2013 - ieeexplore.ieee.org
A multi-channel 3-ps-rms single-shot precision timeto-digital converter (TDC) is presented.
The time interpolation is based on a delay-locked-loop (DLL) employing resistive …

A local passive time interpolation concept for variation-tolerant high-resolution time-to-digital conversion

S Henzler, S Koeppe, D Lorenz… - IEEE Journal of Solid …, 2008 - ieeexplore.ieee.org
Time-to-digital converters (TDCs) are promising building blocks for the digitalization of
mixed-signal functionality in ultra-deep-submicron CMOS technologies. A short survey on …

A high resolution digital CMOS time-to-digital converter based on nested delay locked loops

A Mantyniemi, T Rahkonen… - 1999 IEEE International …, 1999 - ieeexplore.ieee.org
This paper describes an integrated digital CMOS time-to-digital converter, TDC, with sub-
gate-delay LSB width and 50 ps single shot resolution which equals 7 mm in time-of-flight …

Monolithic time-to-digital converter with 20ps resolution

S Tisa, A Lotito, A Giudice… - ESSCIRC 2004-29th …, 2003 - ieeexplore.ieee.org
We present a fully-integrated time-to-digital converter, in a standard 0.8/spl mu/m-CMOS
technology, based on a cyclic pulse-shrinking design, that provides the lowest channel width …

15.5 A 0.6 V 1.17 ps PVT-tolerant and synthesizable time-to-digital converter using stochastic phase interpolation with 16× spatial redundancy in 14nm FinFET …

SJ Kim, W Kim, M Song, J Kim, T Kim… - 2015 IEEE International …, 2015 - ieeexplore.ieee.org
A time-to-digital converter (TDC) is a key element for the digitization of timing information in
modern mixed-signal circuits such as digital PLLs, DLLs, ADCs, and on-chip jitter-monitoring …

A 16 mW 250 ps double-hit-resolution input-sampled time-to-digital converter in 45-nm CMOS

SU Rehman, MM Khafaji, C Carta… - IEEE Transactions on …, 2018 - ieeexplore.ieee.org
Several new approaches for multi-hit delay-line-based time-to-digital converters (TDCs) are
discussed and an input-sampled TDC architecture is realized in 45-nm SOI CMOS. The TDC …

A 2.5-ps bin size and 6.7-ps resolution FPGA time-to-digital converter based on delay wrapping and averaging

P Chen, YY Hsiao, YS Chung… - IEEE Transactions on …, 2016 - ieeexplore.ieee.org
A high-resolution time-to-digital converter (TDC) implemented with field programmable gate
array (FPGA) based on delay wrapping and averaging is presented. The fundamental idea …

A CMOS time-to-digital converter (TDC) based on a cyclic time domain successive approximation interpolation method

A Mantyniemi, T Rahkonen… - IEEE Journal of Solid …, 2009 - ieeexplore.ieee.org
This paper describes a time-to-digital converter (TDC) with~ 1.2 ps resolution and~ 327 mus
dynamic range suitable for laser range-finding application for example. The resolution of …