System-level power-performance trade-offs in bus matrix communication architecture synthesis

S Pasricha, YH Park, FJ Kurdahi, N Dutt - Proceedings of the 4th …, 2006 - dl.acm.org
System-on-chip communication architectures have a significant impact on the performance
and power consumption of modern multi-processor system-on-chips (MPSoCs). However …

[PDF][PDF] System-Level Power-Performance Trade-Offs in Bus Matrix Communication Architecture Synthesis

S Pasricha, YH Park, FJ Kurdahi, N Dutt - 2006 - engr.colostate.edu
System-on-chip communication architectures have a significant impact on the performance
and power consumption of modern multiprocessor system-on-chips (MPSoCs). However …

[PDF][PDF] System-Level Power-Performance Trade-Offs in Bus Matrix Communication Architecture Synthesis

S Pasricha, YH Park, FJ Kurdahi, N Dutt - 2006 - Citeseer
System-on-chip communication architectures have a significant impact on the performance
and power consumption of modern multiprocessor system-on-chips (MPSoCs). However …

System-level power-performance trade-offs in bus matrix communication architecture synthesis

YH Park, FJ Kurdahi, N Dutt… - Proceedings of the 4th …, 2006 - ieeexplore.ieee.org
System-on-chip communication architectures have a significant impact on the performance
and power consumption of modern multiprocessor system-on-chips (MPSoCs). However …

[PDF][PDF] System-Level Power-Performance Trade-Offs in Bus Matrix Communication Architecture Synthesis

S Pasricha, YH Park, FJ Kurdahi, N Dutt - 2006 - researchgate.net
System-on-chip communication architectures have a significant impact on the performance
and power consumption of modern multiprocessor system-on-chips (MPSoCs). However …

[PDF][PDF] System-Level Power-Performance Trade-Offs in Bus Matrix Communication Architecture Synthesis

S Pasricha, YH Park, FJ Kurdahi, N Dutt - 2006 - websrv.cecs.uci.edu
System-on-chip communication architectures have a significant impact on the performance
and power consumption of modern multiprocessor system-on-chips (MPSoCs). However …

[PDF][PDF] System-Level Power-Performance Trade-Offs in Bus Matrix Communication Architecture Synthesis

S Pasricha, YH Park, FJ Kurdahi, N Dutt - 2006 - academia.edu
System-on-chip communication architectures have a significant impact on the performance
and power consumption of modern multiprocessor system-on-chips (MPSoCs). However …

System-level power-performance trade-offs in bus matrix communication architecture synthesis

YH Park, FJ Kurdahi, N Dutt, S Pasricha - … /software codesign and …, 2006 - computer.org
Abstract System-on-chip communication architectures have a significant impact on the
performance and power consumption of modern multi-processor system-on-chips …

[引用][C] System-level power-performance trade-offs in bus matrix communication architecture synthesis

S PASRICHA, YH PARK… - CODES+ ISSS 2006 …, 2006 - pascal-francis.inist.fr
System-level power-performance trade-offs in bus matrix communication architecture
synthesis CNRS Inist Pascal-Francis CNRS Pascal and Francis Bibliographic Databases …

System-level power-performance trade-offs in bus matrix communication architecture synthesis

S Pasricha, YH Park, FJ Kurdahi, N Dutt - … of the 4th International Conference on … - infona.pl
System-on-chip communication architectures have a significant impact on the performance
and power consumption of modern multiprocessor system-on-chips (MPSoCs). However …