1.3 V 20 ps time-to-digital converter for frequency synthesis in 90-nm CMOS
RB Staszewski, S Vemulapalli, P Vallur… - … on Circuits and …, 2006 - ieeexplore.ieee.org
We propose and demonstrate a 20-ps time-to-digital converter (TDC) realized in 90-nm
digital CMOS. It is used as a phase/frequency detector and charge pump replacement in an
all-digital phase-locked loop for a fully-compliant Global System for Mobile Communications
(GSM) transceiver. The TDC core is based on a pseudodifferential digital architecture that
makes it insensitive to nMOS and pMOS transistor mismatches. The time conversion
resolution is equal to an inverter propagation delay, which is the finest logic-level …
digital CMOS. It is used as a phase/frequency detector and charge pump replacement in an
all-digital phase-locked loop for a fully-compliant Global System for Mobile Communications
(GSM) transceiver. The TDC core is based on a pseudodifferential digital architecture that
makes it insensitive to nMOS and pMOS transistor mismatches. The time conversion
resolution is equal to an inverter propagation delay, which is the finest logic-level …
Time-to-digital converter for RF frequency synthesis in 90 nm CMOS
RB Staszewski, S Vemulapalli, P Vallur… - 2005 IEEE Radio …, 2005 - ieeexplore.ieee.org
We propose and demonstrate a 20 ps time-to-digital converter (TDC) in 90 nm digital CMOS.
It is used as a phase/frequency detector and charge pump replacement in an all-digital PLL
for a fully-compliant GSM transceiver. The TDC core is based on a pseudo-differential digital
architecture that makes it insensitive to NMOS and PMOS mismatches. The time conversion
resolution is equal to an inverter propagation delay, which is the finest logic-level
regenerative timing in CMOS. The TDC is self calibrating with estimation accuracy better …
It is used as a phase/frequency detector and charge pump replacement in an all-digital PLL
for a fully-compliant GSM transceiver. The TDC core is based on a pseudo-differential digital
architecture that makes it insensitive to NMOS and PMOS mismatches. The time conversion
resolution is equal to an inverter propagation delay, which is the finest logic-level
regenerative timing in CMOS. The TDC is self calibrating with estimation accuracy better …
以上显示的是最相近的搜索结果。 查看全部搜索结果