By keeping data-intensive applications into consideration, we have investigated the robustness of digital logic circuit design for Computation In-Memory (CiM) using 9T SRAM cells at 22 nm technology nodes. PVT analysis (Process corner, Voltage, and Temperature) is also presented to check the robustness of the circuit. We have proposed a latch-based sense amplifier and voltage reference for 9T SRAM-based CiM architecture. The proposed design is good for demonstrating the logical operation with the memory. A comparison of 250 nm technology against 22 nm is also demonstrated in this work for 9T SRAM-based CiM.