A 1.54 mW/element 150μm-pitch-matched receiver ASIC with element-level SAR/shared-single-slope hybrid ADCs for miniature 3D ultrasound probes
2019 Symposium on VLSI Circuits, 2019•ieeexplore.ieee.org
This paper presents an ultrasound receiver ASIC in 180nm CMOS that enables element-
level digitization of echo signals in miniature 3D ultrasound probes. It is the first to integrate
an analog front-end and a 10-b Nyquist ADC within the 150 μm element pitch of a 5-MHz 2D
transducer array. To achieve this, a hybrid SAR/shared-single-slope architecture is
proposed in which the ramp generator is shared within each 2x2 subarray. The ASIC
consumes 1.54 mW/element and has been successfully demonstrated in an acoustic …
level digitization of echo signals in miniature 3D ultrasound probes. It is the first to integrate
an analog front-end and a 10-b Nyquist ADC within the 150 μm element pitch of a 5-MHz 2D
transducer array. To achieve this, a hybrid SAR/shared-single-slope architecture is
proposed in which the ramp generator is shared within each 2x2 subarray. The ASIC
consumes 1.54 mW/element and has been successfully demonstrated in an acoustic …
This paper presents an ultrasound receiver ASIC in 180nm CMOS that enables element-level digitization of echo signals in miniature 3D ultrasound probes. It is the first to integrate an analog front-end and a 10-b Nyquist ADC within the 150 μm element pitch of a 5-MHz 2D transducer array. To achieve this, a hybrid SAR/shared-single-slope architecture is proposed in which the ramp generator is shared within each 2x2 subarray. The ASIC consumes 1.54mW/element and has been successfully demonstrated in an acoustic imaging experiment.
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