Scaling of MOS technology introduces issues to the memory design like read and write latency, leakage current, reduction in Static Voltage Noise Margin (SVNM), and stability. The parasitic capacitance existing on the bitline can have a significant impact on the memory performance and capacity. This paper discusses the need and working of an improved auxiliary circuit assisted sense amplifier design. The improved sense amplifier design was further used in a case study of 1-Kb memory using conventional 6T SRAM cell. The architecture is designed and implemented in 65-nm CMOS technology with a supply voltage of 0.9 V. The results show that the design achieves the operating frequency of 2.5 GHz with a power consumption of 13.5 mW. Also. the timing margin was improved by 22.3% compared to the strong-arm latch sense amplifier.