A 25–35 GHz neutralized continuous class-F CMOS power amplifier for 5G mobile communications achieving 26% modulation PAE at 1.5 Gb/s and 46.4% peak PAE
IEEE Transactions on Circuits and Systems I: Regular Papers, 2018•ieeexplore.ieee.org
This paper presents a high-efficiency neutralized continuous class-F (CCF) CMOS power
amplifier (PA) design technique for millimeter-wave (mmW) 5G mobile communications. A
parasitic-aware tuned-load with a high-order harmonicresonance network is proposed to
shape the current and voltage waveforms for the CCF PA. At mmW frequencies, the gate-
drain capacitance (Cgd) creates adverse capacitive loading on harmonic-tuned output load
networks. As a result, a CCF PA suffers from compromised power efficiency. To address this …
amplifier (PA) design technique for millimeter-wave (mmW) 5G mobile communications. A
parasitic-aware tuned-load with a high-order harmonicresonance network is proposed to
shape the current and voltage waveforms for the CCF PA. At mmW frequencies, the gate-
drain capacitance (Cgd) creates adverse capacitive loading on harmonic-tuned output load
networks. As a result, a CCF PA suffers from compromised power efficiency. To address this …
This paper presents a high-efficiency neutralized continuous class-F (CCF) CMOS power amplifier (PA) design technique for millimeter-wave (mmW) 5G mobile communications. A parasitic-aware tuned-load with a high-order harmonicresonance network is proposed to shape the current and voltage waveforms for the CCF PA. At mmW frequencies, the gate- drain capacitance (Cgd) creates adverse capacitive loading on harmonic-tuned output load networks. As a result, a CCF PA suffers from compromised power efficiency. To address this, we integrate a transformer with a tunable coupling coefficient between gate-drain of the power-device. This proposed technique allows accurate neutralization of Cgd, reducing detrimental loading effect on harmonic-tuned load while enhancing power efficiency and stability. We fabricated a CCF PA in 65-nm CMOS technology achieving >40% power-added efficiency (PAE) over 33.3% fractional bandwidth (25-35 GHz) and 46.4% peak PAE at 29 GHz. The measured peak saturated output power (Po,sat) is 14.8 dBm at 30 GHz. The PA is tested with 64-quadratureamplitude-modulated signal at a data rate of 1.5 Gb/s. Under this test setup, the PA achieves modulated PAE of 26%/24%/21.4% and average output power (Po,avg) of 9.2/8.8/8.6 dBm at 28, 32, and 34 GHz, respectively, while maintaining better than -25 dB of error vector magnitude and -27 dBc of adjacent channel leakage ratio. To the authors' knowledge, this design presents one of the highest reported PAEs among mmW CMOS PAs.
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