A 56-GHz Fractional-N PLL With 110-fs Jitter
Y Zhao, O Memioglu, L Kong… - IEEE Journal of Solid …, 2022 - ieeexplore.ieee.org
IEEE Journal of Solid-State Circuits, 2022•ieeexplore.ieee.org
A fractional-phase-locked loop (PLL) architecture incorporates a switched-current finite
impulse response (FIR) filter to suppress the modulator () noise. Using a compact, low-
power divide-by-8 circuit and realized in 28-nm CMOS technology, the PLL exhibits a phase
noise of− 98 dBc/Hz at 1-MHz offset in the fractional-mode while consuming 23 mW and
occupying an active area of 0.1 mm 2.
impulse response (FIR) filter to suppress the modulator () noise. Using a compact, low-
power divide-by-8 circuit and realized in 28-nm CMOS technology, the PLL exhibits a phase
noise of− 98 dBc/Hz at 1-MHz offset in the fractional-mode while consuming 23 mW and
occupying an active area of 0.1 mm 2.
A fractional- phase-locked loop (PLL) architecture incorporates a switched-current finite impulse response (FIR) filter to suppress the modulator ( ) noise. Using a compact, low-power divide-by-8 circuit and realized in 28-nm CMOS technology, the PLL exhibits a phase noise of −98 dBc/Hz at 1-MHz offset in the fractional- mode while consuming 23 mW and occupying an active area of 0.1 mm 2.
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