A successive-approximation-register (SAR) analog-to-digital converter (ADC) incorporates “tapered bit periods” to reduce power consumption by minimizing the digital-to-analog converter (DAC) timing overhead. Utilizing a variable delay line and the standard SAR logic, the proposed technique reduces power by downsizing the DAC drivers and digital logic without decreasing the sampling rate. A detailed analysis derives, for the first time, a closed-form solution of the capacitive DAC settling time accounting for parasitics, and determines the time savings of the proposed design. In addition, this brief proposes a “partially interdigitated” DAC layout to reduce the bottom-plate parasitic capacitance to minimize the DAC power. A 9-bit prototype fabricated in 180-nm technology achieves a signal-to-noise-distortion ratio (SNDR) of 55.5 dB at a 10-MHz sampling rate while consuming 28 μW, yielding a figure-of-merit of 5.7 fJ/conversion-step, the lowest among published ADCs at similar speeds and resolutions.