A blocker-tolerant direct sampling receiver for wireless multi-channel communication in 14nm FinFET CMOS
2019 IEEE Asian Solid-State Circuits Conference (A-SSCC), 2019•ieeexplore.ieee.org
This paper presents a low power and area efficient wireless direct sampling receiver (DSR)
implemented in 14nm FinFET process for frequency modulation (FM) receiver. By employing
digital mixer for channel selection, the inductor based local oscillator can be removed, and
I/Q matching requirements in analog front-end are vastly relaxed. Implemented in a 14nm
FinFET process, the proposed FM-DSR with FPGA based demodulation achieves 31 dB
SNR with-90 dBm sensitivity level and 71 dB SNR with-47 dBm input power while …
implemented in 14nm FinFET process for frequency modulation (FM) receiver. By employing
digital mixer for channel selection, the inductor based local oscillator can be removed, and
I/Q matching requirements in analog front-end are vastly relaxed. Implemented in a 14nm
FinFET process, the proposed FM-DSR with FPGA based demodulation achieves 31 dB
SNR with-90 dBm sensitivity level and 71 dB SNR with-47 dBm input power while …
This paper presents a low power and area efficient wireless direct sampling receiver (DSR) implemented in 14nm FinFET process for frequency modulation (FM) receiver. By employing digital mixer for channel selection, the inductor based local oscillator can be removed, and I/Q matching requirements in analog front-end are vastly relaxed. Implemented in a 14nm FinFET process, the proposed FM-DSR with FPGA based demodulation achieves 31 dB SNR with -90 dBm sensitivity level and 71 dB SNR with -47 dBm input power while consuming 11.74 mW.
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