A fully-integrated low phase-noise nested-loop PLL for frequency synthesis
AN Hafez, MI Elmasry - Proceedings of the IEEE 2000 Custom …, 2000 - ieeexplore.ieee.org
AN Hafez, MI Elmasry
Proceedings of the IEEE 2000 Custom Integrated Circuits Conference …, 2000•ieeexplore.ieee.orgIt is greatly beneficial to integrate the VCO. An efficient way to accomplish that is through the
help of wide-bandwidth PLLs. This paper presents a simple nested-loop PLL architecture
that achieves very wide BW while maintaining the required frequency resolution and spur
rejection. The wide-BW loop, including the loop filter, is integrated on a single chip in a 25
GHz bipolar process. The PLL achieves a phase-noise of-100 dBc/Hz at 10 kHz offset from 1
GHz and consumes 9.9 mA from a 3.3 V supply.
help of wide-bandwidth PLLs. This paper presents a simple nested-loop PLL architecture
that achieves very wide BW while maintaining the required frequency resolution and spur
rejection. The wide-BW loop, including the loop filter, is integrated on a single chip in a 25
GHz bipolar process. The PLL achieves a phase-noise of-100 dBc/Hz at 10 kHz offset from 1
GHz and consumes 9.9 mA from a 3.3 V supply.
It is greatly beneficial to integrate the VCO. An efficient way to accomplish that is through the help of wide-bandwidth PLLs. This paper presents a simple nested-loop PLL architecture that achieves very wide BW while maintaining the required frequency resolution and spur rejection. The wide-BW loop, including the loop filter, is integrated on a single chip in a 25 GHz bipolar process. The PLL achieves a phase-noise of -100 dBc/Hz at 10 kHz offset from 1 GHz and consumes 9.9 mA from a 3.3 V supply.
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