A methodology and toolset to enable systemc and VHDL Co-simulation
The new design challenges imposed by the increasing difficulties of today's electronic
systems obligated designers to develop new methodologies. System-level design and
platform-based design are playing an important rule in the electronics industry, and design
reuse is a key concept. SystemC is a design language which is being largely adopted to
raise the abstraction level of hardware design and verification, becoming an important
system design language nowadays. Considering the large amount of VHDL RTL modules …
systems obligated designers to develop new methodologies. System-level design and
platform-based design are playing an important rule in the electronics industry, and design
reuse is a key concept. SystemC is a design language which is being largely adopted to
raise the abstraction level of hardware design and verification, becoming an important
system design language nowadays. Considering the large amount of VHDL RTL modules …
[PDF][PDF] A Methodology and Toolset to Enable SystemC and VHDL Co-simulation.
The new design challenges imposed by the increasing difficulties of today's electronic
systems obligated designers to develop new methodologies. System-level design and
Platform-based design are playing an important rule in the electronics industry, and design
reuse is a key concept. SystemC is a design language which is being largely adopted to
raise the abstraction level of hardware design and verification, becoming an important
system design language nowadays. Considering the large amount of VHDL RTL modules …
systems obligated designers to develop new methodologies. System-level design and
Platform-based design are playing an important rule in the electronics industry, and design
reuse is a key concept. SystemC is a design language which is being largely adopted to
raise the abstraction level of hardware design and verification, becoming an important
system design language nowadays. Considering the large amount of VHDL RTL modules …
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