SR-Latch Physically Unclonable Function (PUF) is the most popular FPGA-based implementation for cryptographic applications. The implementation of a symmetric unbiased SR-Latch PUF is a difficult task due to some restrictions that are imposed on the FPGA implementation. Researchers have proposed different implementation methods which require increasing the area consumption. In this paper, a new design scheme has been introduced to overcome this problem. Two different methods for generating PUF responses are employed in our proposed work. In the first method, which is called method A, the SR-Latch output in its stable state is used to generate challenge-response pairs. In the second method, which is called method B, the two most significant bits of the mean value of oscillations is counted during the metastable state of the SR-Latch to form the PUF responses. In order to analyze the proposed PUF, we implement the proposed scheme on six Spartan-3 FPGA boards. The experimental results show that the average uniqueness of our approach is close to 50%. It is also demonstrated that the area consumption in the design scheme is at least three times better than the conventional methods. The proposed SR-Latch PUF generates responses with high entropy which is suitable for hardware security applications.