… In this letter, we propose a new structure of SOT-MRAM design that improves integration
density while maintaining inherent advantages such as reliability associated with MTJ and …

… To popularize the bit-cell design with a practical SOT device, in this paper, the SOT-MRAM
design rules which adopt the technically-feasible top-pinned SOT-MTJ and fully consider the …

… SOT-MRAM design by reducing the vertical and horizontal dimensions. The proposed
SOT-MRAM is designed … two-transistor-based design of conventional SOT-MRAM. Moreover, the …

… read and write routes allows SOT-MRAM to have a lower error … SOT-MRAM can take
advantage of 3D stacking to reduce power and latency. More importantly, the density of SOT-MRAM …

… For the write current simulations considering peripheral circuits as well as cell structure,
we designed 512 × 512 SOT-MRAM macro using 28nm technology with 0.9V supply voltage. …

… In this work, we proposed a novel SOT-MRAM bit cell design with 3 transistors sharing 4
diffusion regions. By including all transistors in supplying current for SOT effect, transistor width …

… an area-optimized cell design that achieved a remarkable area optimization of 42%. Also, a
similar pioneering area-optimized SOTMRAM … highdensity, area-optimized, and performance-…

Complementary polarized spin-transfer torque magnetic random-access memory (CPSTT-MRAM)
has been proposed to address the sensing reliability issues caused by the single-…

In this paper, we propose a novel Spin Orbit Torque Magnetic Random Access Memory (SOT-MRAM)
array design that could simultaneously work as non-volatile memory and …

… 340 mV–1.1 V, 289 Gbps/W, 2090-gate nanoAES hardware accelerator with area-optimized
encrypt/decrypt GF (2 4) 2 polynomials in 22 nm tri-gate CMOS. IEEE Journal of Solid-State …