DFGNet: Mapping dataflow graph onto CGRA by a deep learning approach

S Yin, D Liu, L Sun, L Liu, S Wei - 2017 IEEE international …, 2017 - ieeexplore.ieee.org
2017 IEEE international symposium on circuits and systems (ISCAS), 2017ieeexplore.ieee.org
The coarse-grained reconfigurable architecture (C-GRA) is a promising platform that
provides both high performance and high power-efficiency. Dataflow graph (DFG) mapping
is critical to tap the potentials of CGRAs. Inspired from the great progress made in tree
search game using deep neural network, we proposed a frame work for learning
convolutional neural network for mapping DFGs onto spatial programmable CGRAs.
Considering the mapping process, we present a dual-input neural network capturing the …
The coarse-grained reconfigurable architecture (C-GRA) is a promising platform that provides both high performance and high power-efficiency. Dataflow graph (DFG) mapping is critical to tap the potentials of CGRAs. Inspired from the great progress made in tree search game using deep neural network, we proposed a frame work for learning convolutional neural network for mapping DFGs onto spatial programmable CGRAs. Considering the mapping process, we present a dual-input neural network capturing the features from both DFGs in applications and Process Element Array (PEA) in CGRA. In order to train the neural network, algorithms are designed to automatically generate a data set from PEA intermediate states of preprocessed DFG. Finally, experimental results demonstrate that our proposed mapping approach is competitive with state-of-the-art DFG mapping algorithms in performance while the compilation time is greatly reduced.
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