[引用][C] Design of Efficient Low power 9T SRAM cell
K Gavaskar, S Priya - International Journal of Engineering Research and …, 2013
[PDF][PDF] Design of efficient low power 9T SRAM cell
K Priya, K Gavaskar - International Journal of Engineering, 2013 - academia.edu
Memory is the most common part in CMOS IC's applications. The power consumption and
speed of SRAMs are important issue that has led to multiple designs with the purpose of
minimizing the power consumption during both read and write operations. In this paper, a
novel 9T static random access memory (SRAM) cell design which consumes less dynamic
power and has high read stability is predicted. This paper also includes the SRAM array
structure, it consist of sense amplifier and address decoders. The Tanner EDA tool is used …
speed of SRAMs are important issue that has led to multiple designs with the purpose of
minimizing the power consumption during both read and write operations. In this paper, a
novel 9T static random access memory (SRAM) cell design which consumes less dynamic
power and has high read stability is predicted. This paper also includes the SRAM array
structure, it consist of sense amplifier and address decoders. The Tanner EDA tool is used …
以上显示的是最相近的搜索结果。 查看全部搜索结果