Design of low power 5-bit hybrid flash ADC
SM Mayur, RK Siddharth, YBN Kumar… - 2016 IEEE Computer …, 2016 - ieeexplore.ieee.org
In this paper, a low power 5-bit hybrid flash architecture is proposed. The proposed analog-
to-digital converter (ADC) uses appropriate combination of both conventional double-tail
comparators and standard cell comparators. Standard cell comparators are used to reduce
power consumption. Thus, the proposed hybrid architecture results in extended dynamic
range when compared to standard cell and thresholdinverter quantization (TIQ) based flash
ADC. The proposedhybrid architecture is implemented in CMOS 180 nm N-welltechnology …
to-digital converter (ADC) uses appropriate combination of both conventional double-tail
comparators and standard cell comparators. Standard cell comparators are used to reduce
power consumption. Thus, the proposed hybrid architecture results in extended dynamic
range when compared to standard cell and thresholdinverter quantization (TIQ) based flash
ADC. The proposedhybrid architecture is implemented in CMOS 180 nm N-welltechnology …
[引用][C] Design of low power 5-Bit hybrid flash ADC
RK Siddharth, KYB Nithin, MH Vasantha - Proceedings of the IEEE Computer Society …, 2016
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