Recent works 1 show that delays introduced in the issue and bypass logic will become
critical for wide issue superscalar processors. One of the proposed solutions is clustering the
processor core. Clustered architectures benefit from a less complex partitioned processor
core and thus, incur in less critical delays. In this paper, we propose a dynamic instruction
steering logic for these clustered architectures that decides at decode time the cluster where
each instruction is executed. The performance of clustered architectures depends on the …