Dynamic management of scratch-pad memory space
Proceedings of the 38th annual Design Automation Conference, 2001•dl.acm.org
Optimizations aimed at improving the efficiency of on-chip memories are extremely
important. We propose a compiler-controlled dynamic on-chip scratch-pad memory (SPM)
management framework that uses both loop and data transformations. Experimental results
obtained using a generic cost model indicate significant reductions in data transfer activity
between SPM and off-chip memory.
important. We propose a compiler-controlled dynamic on-chip scratch-pad memory (SPM)
management framework that uses both loop and data transformations. Experimental results
obtained using a generic cost model indicate significant reductions in data transfer activity
between SPM and off-chip memory.
Optimizations aimed at improving the efficiency of on-chip memories are extremely important. We propose a compiler-controlled dynamic on-chip scratch-pad memory (SPM) management framework that uses both loop and data transformations. Experimental results obtained using a generic cost model indicate significant reductions in data transfer activity between SPM and off-chip memory.
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