This paper presents an extended analysis of TO-packaged SiC power MOSFETs after power cycling (PC) tests. Namely, it is shown that initially present voids in soft lead-based solder die attach disappear not only after certain number of active PC tests, but also after thermal shock tests. Hereby, the conclusion that solder die attach is not the weak spot of SiC power MOSFET packages with an epoxy mold compound (EMC) encapsulation is further supported. Furthermore, an electro-thermo-mechanical (ETM) model developed in-house is used to correlate the dominant wear-out failure of bond wires to the PC test parameters such as heating current, temperature amplitude, and heating on-time, as well as to the thickness of top source die metallization.