[PDF][PDF] Flexible Redundancy in Robust Processor Architecture
T Miller, N Surapaneni, R Teodorescu… - Workshop on Energy …, 2009 - researchgate.net
T Miller, N Surapaneni, R Teodorescu, J Degroat
Workshop on Energy-Efficient Design (WEED), in conjunction with ISCA, 2009•researchgate.netThis paper proposes a reliable processor architecture that dynamically adapts the amount of
protection to the characteristics of an individual chip and its runtime behavior. This
architecture uses fine-grain redundancy, voltage scaling and timing speculation to adapt to
variation and tolerate timing, soft and hard errors. The goal is to provide reliability with a
minimum of resources. Our evaluation shows dynamic adaptation of voltage and
redundancy can reduce the energy delay product (ED) by up to 19% compared to a static …
protection to the characteristics of an individual chip and its runtime behavior. This
architecture uses fine-grain redundancy, voltage scaling and timing speculation to adapt to
variation and tolerate timing, soft and hard errors. The goal is to provide reliability with a
minimum of resources. Our evaluation shows dynamic adaptation of voltage and
redundancy can reduce the energy delay product (ED) by up to 19% compared to a static …
This paper proposes a reliable processor architecture that dynamically adapts the amount of protection to the characteristics of an individual chip and its runtime behavior. This architecture uses fine-grain redundancy, voltage scaling and timing speculation to adapt to variation and tolerate timing, soft and hard errors. The goal is to provide reliability with a minimum of resources. Our evaluation shows dynamic adaptation of voltage and redundancy can reduce the energy delay product (ED) by up to 19% compared to a static architecture with the same error protection.
researchgate.net
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