In Digital Signal Processor (DSP) the arithmetic elements are playing a major vital role in processing the data in processors. The multiplier is the most complex part of the arithmetic circuits which is used in DSP applications. The partial product generation is reducing the speed of the overall multiplier operation in the processor. The computation of partial products for the multiplier is a critical part of hardware implementation. In this paper, we reduce the computational complexity in the proposed buffer based parallel multiplier which occurs in partial product generation. The proposed 16 × 16 multipliers is designed using a tri-state buffer, adder, shifter and multiplexer. The power and delay analysis are observed and compared with existing multipliers. The main and sub-modules are simulated using the Altera EDA tool and implemented using the Altera Cyclone II FPGA family.