This paper focuses on the influence of chip parameters spread on power loss sharing of paralleled SiC MOSFETs. A simulation model of paralleled SiC MOSFETs under switching test is developed for analyzing the relationship between power loss distribution and chip parameter spread. The corresponding physical testbench is built for experimental verification. The spread of different chip parameters, including transfer curve, on-state resistance, internal gate resistance, gate-source capacitance, gate-drain capacitance, drain-source capacitance, from a sample of 30 SiC MOSFET discrete devices were tested. The power loss distribution among the paralleled devices was analyzed under different equivalent switching frequencies. The experimental and simulating results show that transfer curve and on-state resistance are the main parameters that affect power loss sharing. Moreover, the influence of different parameters on power loss can be compensated to reduce the power loss unbalance under different switching frequency.