This paper studies the spread of devices parasitic capacitances and its influence on transient current distribution of paralleled SiC MOSFET devices. First, a sample of 30 SiC MOSFET devices from the same production batch is selected. The C-V characterizations of three critical parasitic capacitances are analyzed in detail for all selected devices. Then, the effects of the variation of three parasitic capacitances on the transient current difference between two paralleled devices under two driver concepts, fully decoupling driver concept (FDDC) and partly decoupling driver concept (PDDC), are deduced theoretically. The sensitivity of transient current imbalance to variations in the parasitic capacitances under FDDC and PDDC is quantitatively calculated by simulation. It is observed that the gate-source capacitance has the most significant influence due to its large variation and the effects of other capacitances are very small. Moreover, the impact of the variation of gate-source capacitance can be reduced by adopting PDDC. Finally, the test bench with symmetrical layout is built for SiC MOSFETs paralleling and a cross-transposition method is proposed to validate the uniformity of the layout. The results obtained by theoretical and simulation analysis are satisfactorily verified by experiments.