Integrated asynchronous ultrawideband impulse radio with intrinsic clock and data recovery
This letter reports an integrated ultrawideband impulse radio design. The proposed radio
applies a combination of frequency-shift keying and ON-OFF keying to realize intrinsic clock
and data recovery as well as asynchronous wireless communication. The transmitter uses
frequency-hopping and duty-cycling methods to achieve ultrawide bandwidth. Both of the
transmitter and the receiver are fabricated on IBM 0.18-μm CMOS process. The chip core
area is 0.031 mm 2 for the transmitter and 0.017 mm 2 for the receiver. The measured power …
applies a combination of frequency-shift keying and ON-OFF keying to realize intrinsic clock
and data recovery as well as asynchronous wireless communication. The transmitter uses
frequency-hopping and duty-cycling methods to achieve ultrawide bandwidth. Both of the
transmitter and the receiver are fabricated on IBM 0.18-μm CMOS process. The chip core
area is 0.031 mm 2 for the transmitter and 0.017 mm 2 for the receiver. The measured power …
This letter reports an integrated ultrawideband impulse radio design. The proposed radio applies a combination of frequency-shift keying and ON-OFF keying to realize intrinsic clock and data recovery as well as asynchronous wireless communication. The transmitter uses frequency-hopping and duty-cycling methods to achieve ultrawide bandwidth. Both of the transmitter and the receiver are fabricated on IBM 0.18-μm CMOS process. The chip core area is 0.031 mm 2 for the transmitter and 0.017 mm 2 for the receiver. The measured power consumption is 2.89mW for the transmitter and 5.4mW for the receiver at the data rate of 3Mb/s. The sensitivity at 1.3 ×10 -3 bit error rate, 2.5Mb/s, and 10.42-ns pulsewidth is -60dBm.
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