Logarithm-approximate floating-point multiplier is applicable to power-efficient neural network training

TY Cheng, Y Masuda, J Chen, J Yu, M Hashimoto - Integration, 2020 - Elsevier
… , floating-point representation is more suitable. This paper proposes to adopt a logarithm-approximate
multiplier … , where LAM approximates a floating-point multiplication as a fixed-point …

Logarithm-approximate floating-point multiplier

S Rezaei, R Omidi, A Azarpeyvand - Microelectronics Journal, 2022 - Elsevier
… This paper proposes an efficient inexact floating-point (FP) multiplier using the idea of a … a
logarithm-approximate FP multiplier, which uses an approximate adder instead of multiplying

PLAM: A posit logarithm-approximate multiplier

R Murillo, AA Del Barrio, G Botella… - … on Emerging Topics …, 2021 - ieeexplore.ieee.org
floating-point counterparts. This article proposes a Posit Logarithm-Approximate Multiplication
(PLAM) scheme to significantly reduce the complexity of posit multipliers, one of the most …

Minimizing power for neural network training with logarithm-approximate floating-point multiplier

TY Cheng, J Yu, M Hashimoto - 2019 29th international …, 2019 - ieeexplore.ieee.org
… proposes to adopt logarithmapproximate multiplier (LAM) for … LAM approximates a floating-point
multiplication as an addition … ing engine, floating-point unit, logarithmic multiplier, multiply…

A logarithmic floating-point multiplier for the efficient training of neural networks

Z Niu, H Jiang, MS Ansari, BF Cockburn, L Liu… - Proceedings of the 2021 …, 2021 - dl.acm.org
… In this paper, a floating-point logarithmic multiplier (FPLM) is proposed for the complex FP
multiplication with simple arithmetic operations. The evaluation results show that the FPLM …

A design framework for hardware-efficient logarithmic floating-point multipliers

T Zhang, Z Niu, J Han - IEEE Transactions on Emerging Topics …, 2024 - ieeexplore.ieee.org
… in floating-point (FP) multiplication can significantly reduce the hardware complexity of a
multiplier. … Hashimoto, “Logarithm-approximate floating-point multiplier is applicable to power-…

Logarithm-approximate floating-point multiplier for hardware-efficient inference in probabilistic circuits

L Yao, M Trapp, K Periasamy, J Leslin… - The 6th Workshop on …, 2023 - openreview.net
… with PCs typically requires 30 – 40 floating-point bits [22, 20] as … In this work, we propose to
approximate floating-point mul… can reduce the hardware cost of multiplication by a factor of up …

On the design of iterative approximate floating-point multipliers

A Towhidy, R Omidi… - IEEE Transactions on …, 2022 - ieeexplore.ieee.org
… Abstract—Approximate multipliers provide power and … floating-point multipliers based
on two-dimensional pseudo-Booth encoding: floating-point pseudo-Booth (PB), and floating-point

Hardware-Efficient Logarithmic Floating-Point Multipliers for Error-Tolerant Applications

Z Niu, T Zhang, H Jiang, BF Cockburn… - IEEE Transactions on …, 2023 - ieeexplore.ieee.org
… -efficient logarithmic floating-point (FP) multipliers are … and more costly conventional FP
multipliers. Radix-4 logarithms are … Hashimoto, “Logarithmapproximate floating-point multiplier

Area-Efficient Iterative Logarithmic Approximate Multipliers for IEEE 754 and Posit Numbers

S Kim, CJ Norris, JI Oelund… - IEEE Transactions on …, 2024 - ieeexplore.ieee.org
… Abstract—The IEEE 754 standard for floating-point (FP) arithmetic is widely used for real …
Instead, the noniterative posit logarithm-approximate multiplier (PLAM) with the same ⟨nb, …