Low-cost FPGA hardware implementation of matrix converter switch control
R Wiśniewski, G Bazydło… - IEEE Transactions on …, 2018 - ieeexplore.ieee.org
IEEE Transactions on Circuits and Systems II: Express Briefs, 2018•ieeexplore.ieee.org
An idea for a hardware realization of a space vector modulation in the direct matrix converter
is proposed in this brief. The method is oriented toward the implementation in a low-cost
field programmable gate arrays (FPGAs). The traditional algorithms usually involve digital
signal processors, which drive the large number of power transistors and “non-standard
positions of control pulses” during the switching sequence. Thus, hardware implementations
have become popular since particular operations are performed faster and more efficiently …
is proposed in this brief. The method is oriented toward the implementation in a low-cost
field programmable gate arrays (FPGAs). The traditional algorithms usually involve digital
signal processors, which drive the large number of power transistors and “non-standard
positions of control pulses” during the switching sequence. Thus, hardware implementations
have become popular since particular operations are performed faster and more efficiently …
An idea for a hardware realization of a space vector modulation in the direct matrix converter is proposed in this brief. The method is oriented toward the implementation in a low-cost field programmable gate arrays (FPGAs). The traditional algorithms usually involve digital signal processors, which drive the large number of power transistors and “non-standard positions of control pulses” during the switching sequence. Thus, hardware implementations have become popular since particular operations are performed faster and more efficiently. This brief proposes a novel hardware algorithm for a matrix converter switch control. Contrary to the existing hardware methods, the presented technique does not require specialized modeling tools, nor advanced converters to achieve the hardware representation. Furthermore, the proposed solution permits concurrent computation of most operations. The method has been verified experimentally. The results of the hardware implementation in a low-cost FPGA are discussed.
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