Low-Power FPGA-Implementation of atan(Y/X) Using Look-Up Table Methods for Communication Applications
R Gutierrez, J Valls - Journal of Signal Processing Systems, 2009 - Springer
Journal of Signal Processing Systems, 2009•Springer
This paper presents an architecture for the computation of the atan (Y/X) operation suitable
for broadband communication applications where a throughput of 20 MHz is required. The
architecture takes advantage of embedded hard-cores of the FPGA device to achieve lower
power consumption with respect to an atan (Y/X) operator based on CORDIC algorithm or
conventional LUT-based methods. The proposed architecture can compute the atan (Y/X)
with a latency of two clock cycles and its power consumption is 49% lower than a CORDIC …
for broadband communication applications where a throughput of 20 MHz is required. The
architecture takes advantage of embedded hard-cores of the FPGA device to achieve lower
power consumption with respect to an atan (Y/X) operator based on CORDIC algorithm or
conventional LUT-based methods. The proposed architecture can compute the atan (Y/X)
with a latency of two clock cycles and its power consumption is 49% lower than a CORDIC …
Abstract
This paper presents an architecture for the computation of the atan(Y/X) operation suitable for broadband communication applications where a throughput of 20 MHz is required. The architecture takes advantage of embedded hard-cores of the FPGA device to achieve lower power consumption with respect to an atan(Y/X) operator based on CORDIC algorithm or conventional LUT-based methods. The proposed architecture can compute the atan(Y/X) with a latency of two clock cycles and its power consumption is 49% lower than a CORDIC or 46% lower than multipartite approach.
Springer
以上显示的是最相近的搜索结果。 查看全部搜索结果