In this present paper, the SOI FINFET structure consists of three regions such that in each region, a potential function is created by implying boundary conditions upon Poisson’s equation. The parabolic potential profile for different regions is computed via bias at the gate/drain region. This work studies the mathematical modeling of silicon on insulator (SOI) FinFET and the impact of h_fin variations (1.4,1.1,0.8,0.3) and W_fin variations (1.1,0.7,0.3) on device performance metrics including low-frequency metrics such as transconductance g_m, Drain conductance g_d, Gate capacitance C_gg and gain in voltage A_v. The simulations carried out using the SILVACO tool reflect that The device has shown optimum performance for (i) $${Q}_{i,S}=\kern0.5em {C}_{ox}\left({V}_{gs}-{V}_{fb}-{\upvarphi}_S\right)-{Q}_{bulk}$$ value by maximizing device gain and operatable frequency; (ii) W_fin = 0.7 value by enhancing the improving device intrinsic resistance, A_v, and VEA, thus making the device operate without any substrate effect. The analysis has clearly distinguished that variation in device size can provide different performances such that higher devices are preferred for superior current drivability, and smaller devices can reduce SCEs bringing more device immunization. After analysis, the drain current results are validated with respect to numerical solutions acquired via a 2-D device simulator giving a similar match.