In this tutorial brief, we introduce a unified wideband phase-noise theory framework of frequency synthesis based on a multirate timestamp modeling with “two -variables”. We apply it to model and analyze two types of ultra-low jitter (i.e., sub-50fs) phase-locking techniques: 1) high-bandwidth PLLs with high phase-detector gain (with emphasis on all-digital PLLs), and 2) injection locking (IL) or recently proposed charge-sharing locking (CSL), serving as a unified guide on achieving the sub-50 fs jitter. All analytical results are numerically verified through time-domain behavioral simulations, demonstrating that the theoretically maximum bandwidths are around 30% and 44% of the reference frequency in PLLs and IL, respectively.