Clock signal have been a great source of power dissipation in synchronous circuits because of high frequency and load. So, by using clock gating one can save power by reducing unnecessary switching activity inside the gated module. Here four gating methods are discussed and their power dissipation is compared. The most popular is synthesis-based, deriving clock enabling signals based on the logic of the underlying system. It unfortunately leaves the majority of the clock pulses driving the flip flops (FFs) redundant. A data driven method stops most of those and yields higher power savings, but its implementation is complex and application dependent. A third method called auto gated FFs (AGFF) is simple but yields relatively small power savings. Another novel method called Look Ahead Clock Gating (LACG) is presented, which combines all the three. It avoids the tight timing constraints of AGFF and data driven by allotting a full clock cycle for the computation of the enabling signals and their propagation.