Pipeline processing in real-time of CABAC decoder based on FPGA
A Petrovsky, A Stankevich… - … Conference on Signals …, 2012 - ieeexplore.ieee.org
A Petrovsky, A Stankevich, A Petrovskyi
2012 International Conference on Signals and Electronic Systems …, 2012•ieeexplore.ieee.orgThis paper presents the implementation on the FPGA module CABAC decoder for h. 264.
The organization of the computational process is based on the pipe-line architecture that
allows to simultaneously decoding multiple bins. This scheme is implemented on FPGA with
clock frequency equal 96MHz and provides decoding of one bin per cycle.
The organization of the computational process is based on the pipe-line architecture that
allows to simultaneously decoding multiple bins. This scheme is implemented on FPGA with
clock frequency equal 96MHz and provides decoding of one bin per cycle.
This paper presents the implementation on the FPGA module CABAC decoder for h.264. The organization of the computational process is based on the pipe-line architecture that allows to simultaneously decoding multiple bins. This scheme is implemented on FPGA with clock frequency equal 96MHz and provides decoding of one bin per cycle.
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