We report on the capacitive memory of the WO₃ nanowire (NW) MOS capacitor on Si substrate synthesized by glancing angle deposition (GLAD) technique inside an electron beam evaporator system. The field-emission gun scanning electron microscope (FEG-SEM) image shows the growth of vertically aligned WO₃ NW with length of ~ 272.8 nm. The capacitance (C)–voltage (V) and conductance (G)–voltage (V) measurements were carried out at room temperature and in the range of 100 kHz to 1 MHz. The interface state density was also calculated and found to be 4.54 × 10¹⁰ eV⁻¹cm⁻² at 1 MHz. The electrical property such as series resistance (Rs) was also estimated. The calculated charge trap state density per area (N) is in the order of 10¹² cm⁻², and the mechanism was attributed to flat-band voltage. The WO₃ NW device exhibits a memory window of ~ 5.96 V at ± 10 V. Good data retention up to 10³ s and endurance up to 100 DC cycles at a read voltage of + 4.7 V were observed. A resistance ratio of approximately 3.34 was also estimated for the device.